1. Field of the Invention
This invention relates to a clocked memory formed on a semiconductor substrate and more specifically a clocked memory with an improved sense driver for a dynamic sense amplifier.
2. Description of the Prior Art
Conventional static memories formed on semiconductor substrates have been produced by using semiconductor technology, especially metal oxide semiconductor (MOS) technology. In such memories, a plurality of memory cells are arranged in a matrix on a semiconductor substrate, e.g., a silicon wafer with each memory cell connected to a word select line and a pair of bit lines formed on the substrate. Frequently, the memory cells each include a latch or flip-flop circuit formed by MOS transistors. The word select lines are connected to and selected by a row address decoder and each pair of bit lines are connected to and selected by a column address decoder. A latch or dynamic presense amplifier is connected between the pair of bit lines to detect a signal from the selected memory cell in each column. The signal from the selected memory cell is finally amplified by a sense amplifier commonly connected to data lines which are connected to each bit line in each column.
With dynamic memories significant difficulties have been encountered in detecting the signal. This is due to the fact that the signal is frequently considerably smaller than a required output level, usually 5 volts. In dealing with such a small signal, it need be given special consideration for driving the presence amplifier which is to gradually enable the presense amplifier to ensure detection of the signal.
Heretofore, in the early stages of designing the detection circuitry for the memories, a multi-phase clock generator was provided to drive the decoders and the presense amplifiers separately. However, it was necessary to delay a clock signal sufficiently to drive the presense amplifier in the multi-phase clock generator. This was due to the fact that the clock signal was not tracked with a decode clock for driving the decoders. Therefore, it results in enlarging the access time.
Recently, a unique design of the static memory circuit was introduced in which a reference row was created with resistance and capacitive loading equal to that on the word select lines. The reference row is a part of the memory matrix and comprised of a reference line loaded with a pair of the transistors in each column which represent the cell loading. A buffer amplifier is connected to the end of the reference line and the buffered output is in turn connected to each presense amplifier in each column. A reference row driver is clocked by the same clock signal as the decoder and supplied to the reference line. The above circuit design is illustrated in an article of IEEE Journal of Solid-State Circuits, Volume SC-11, No. 5, October 1976, entitled "Two 4K Static 5-V RAM's." It is noted that the above circuit requires the reference row and the buffer amplifier.